Checksum O.K !!! Boot with zImage Starting kernel. Download Done!! Download Address: 0xc0008000, Download Filesize:0x20f098 Now, Checksum calculation. I'm just hoping the FPGA is big enough.Ĭode: Now, Downloading Please waiting. Basically, I want to make this thing as close to as the Agilent TrueForm generators in functionality as possible. There is also the 16 bit digital output that will have to read from somewhere. Also, I plan on supporting at least 4 internal channels - two main ones, and at least one more 'sub channel' per main channel for arbitrary AM, FM, PM, FSK, PSK, etc. There should be enough memory bandwidth to run both DAC channels from one memory controller - wouldn't it be great to have an unequal split and have >64Mpts accessible to one channel while still being able to use the other channel? That's basically what I'm hoping to do - anything can read from anywhere.

I also want to run the memory as fast as possible as there are multiple things that need to have access and I want to make sure nothing gets starved.

This should be relatively easy to arrange as the memory controller ports can all be placed in independent clock domains. Take a look at clock.v in the repo right now I am in the process of getting all of the clock switching logic working right now. So the memory controller and some of the logic will run off of the internal osc, and the DSP/DDS/DAC logic will run off of a switched reference input.

I considered this, but the thing is that the unit has two frequency references - one internal and one external - and the FPGA needs to be able to switch between them without resetting the memory controller.

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